Nec Network Controller uPD98502 Manual de usuario Pagina 496
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APPENDIX A MIPS III INSTRUCTION SET DETAILS
496
Preliminary User’s Manual S15543EJ1V0UM
HIBERNATE
Hibernate
HIBERNATE
CO
1
COP0
0 1 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HIBERNATE
1 0 0 0 1 1
31 26 25 24 6 5 0
61 19 6
Format:
HIBERNATE
Description:
HIBERNATE instruction starts mode transition from Fullspeed mode to Hibernate mode.
When the HIBERNATE instruction finishes the WB stage, the processor wait by the SysAD bus is idle state, after
then the internal clocks and the system interface clocks will shut down, thus freezing the pipeline.
Cold Reset causes the Hibernate mode to the Fullspeed mode transition.
Operation:
32, 64 T:
T+1: Hibernate operation ()
Exceptions:
Coprocessor unusable exception
- Preliminary User’s Manual 1
- NOTES FOR CMOS DEVICES 4
- M5D 98. 12 5
- LIST OF FIGURES (1/5) 16
- LIST OF FIGURES (2/5) 17
- LIST OF FIGURES (3/5) 18
- LIST OF FIGURES (4/5) 19
- LIST OF FIGURES (5/5) 20
- LIST OF TABLES (1/2) 21
- LIST OF TABLES (2/2) 22
- CHAPTER 1 INTRODUCTION 23
- 1.1 Features 23
- 1.2 Ordering Information 23
- 1.3 System Configuration 24
- 1.4 Block Diagram (Summary) 25
- 1.5 Block Diagram (Detail) 26
- Ethernet Controller 30
- USB CONTROLLER 31
- Index Mark 33
- Pin Name 34
- 1.7 Pin Function 37
- 1.7.5 Memory interface 39
- 1.7.6 PCI interface 41
- 1.7.7 ATM interface 43
- 1.7.8 Ethernet interface 45
- 1.7.9 USB interface 46
- 1.7.10 UART interface 47
- 1.7.11 Micro Wire interface 47
- 1.7.14 I.C. – open 48
- 1.7.15 I.C.– pull down 48
- 1.7.17 I.C. – pull up 48
- Register 49
- 1.9 Memory Map 53
- 1.10 Reset Configuration 54
- 1.12 Clock Control Unit 56
- 4120A Core 57
- 2.3 Pipeline 84
- If they are 90
- . The result 92
- 2.4 Memory Management System 101
- is then added to the PFN 102
- CHAPTER 2 V 103
- VPN Offset 105
- is passed to 105
- Without TLB mapping 111
- (a) 32-bit mode 118
- (b) 64-bit mode 118
- 1819 031 11 10 121
- 0 MASK 0 121
- 2.5 Exception Processing 129
- 161718192021222324 135
- 0 BEV TS SR 0 CH CE DE 135
- 11111112 135
- 3 2 1 031 139
- PAddr0 0 R W 139
- WatchLo Register 139
- 0 Diagnostic 140
- Cold Reset 142
- (Unmapped, cacheable space) 161
- (Unmapped, uncached space) 161
- (Hardware) 163
- (Software) 163
- 2.6 Initialization Interface 165
- 2.7 Cache Memory 168
- 2.7.6 Cache data integrity 174
- Valid bit Clear 175
- Tag Read to TagLo 176
- W bit Read to TagLo 176
- Data cache only 176
- Tag Write 177
- Write-back (see 179
- Figure 2-84) 179
- Figure 2-84. Writeback Flow 180
- Figure 2-85. Refill Flow 180
- 2.8 CPU Core Interrupts 182
- 3.1 Overview 185
- System Controller 187
- 3.1.10 Data flow diagram 188
- 3.2 Registers 189
- 3.3 CPU Interface 201
- Remark VR 202
- 3.4 Memory Interface 204
- Normal ROM Read Cycle 208
- FLASH M em ory W rite Cycle 208
- ROM Burst Read Cycle 208
- Example (8 MB PROM) 215
- (System Controller) 215
- Example (4 MB FLASH) 215
- SDRAM Configuration 218
- 3.5 IBUS Interface 221
- 3.6 DSU (Deadman’s SW Unit) 224
- Big-Endian 227
- Little-Endian 227
- 4.1 Overview 229
- ATM Cell Processor 230
- 4120A RISC Processor 232
- SDRAM Space 236
- 4.3 Interruption 237
- 4.5 Data Structure 247
- - Tx buffer directory 248
- - Tx link pointer 248
- - Tx buffer descriptor 248
- - Tx packet descriptor 248
- -Tx link pointer 250
- -Tx buffer descriptor 250
- -Rx buffer directory 252
- -Rx link pointer 252
- -Rx buffer descriptor 252
- -Rx pool descriptor 252
- Alert level 253
- 4.6 Initialization 255
- 00_0000H 256
- 0F_FFFFH 256
- 00_2000H 256
- 4.7 Commands 257
- 4.8 Operations 262
- Work RAM (10 Kbytes) 263
- NEXT POINTER 265
- CELL HEADER 265
- PACKET DESCRIPTOR STORAGE 265
- (3) Tx VC table 267
- Figure 4-28. Tx VC Table 267
- (1) Rx VC table 271
- A_MWA[3:0] 276
- A_MTA[3:0] 276
- A_MBA[3:0] 276
- A_MSA[3:0] 276
- 5.1 Overview 277
- Transceiver 278
- Ethernet Controller Block 278
- Register Categories 279
- Tx_FIFO (256 Bytes) 295
- To MAC Control Block 295
- From internal bus 295
- Rx_FIFO (256 Bytes) 297
- To internal bus 297
- From MAC Control Block 297
- 5.3 Operation 300
- Set RCVDP 306
- CHAPTER 6 USB CONTROLLER 309
- 6.1 Overview 309
- 6.2 Registers 311
- 6.3 USB Attachment Sequence 330
- 6.4 Initialization 331
- Data Segment 334
- Tx Packet 335
- -Tx Buffer Directory 336
- -Tx Link Pointer 336
- -Tx Buffer Descriptor 336
- 4120A when transmitting data 338
- Figure 6-7. V 338
- Buffer Directory 345
- -Rx Buffer Directory 346
- -Rx Link Pointer 346
- -Rx Buffer Descriptor 346
- 6.7 Power Management 364
- 6.8 Receiving SOF Packet 367
- Tx data Rx data 368
- 6.10 Example of Connection 369
- CHAPTER 7 PCI CONTROLLER 370
- 7.1 Overview 370
- 7.2 Bus Bridge Functions 371
- CHAPTER 7 PCI CONTROLLER 382
- PCI-Host 384
- Controller 384
- Internal 384
- 7.4 Functions in Host-mode 386
- AD[31:0] 388
- PCI device 388
- Register Name 390
- Register Name Size 402
- 7.5.19.2 Vendor ID register 403
- 7.5.19.3 Device ID register 403
- 7.5.19.4 Command register 404
- 7.5.19.5 Status register 405
- 7.5.19.23 PMCSR register 410
- 7.5.19.24 PMData register 410
- 7.6 Information for Software 411
- NS16550D 414
- 8.3 Registers 415
- CHAPTER 9 TIMER 424
- 9.1 Overview 424
- 9.2 Block Diagram 424
- 9.3 Registers 425
- CHAPTER 10 MICRO WIRE 427
- 10.1 Overview 427
- 10.2 Operations 428
- 10.3 Registers 429
- A.5 CPU Instruction 435
- 0 0 1 0 0 0 437
- Add Immediate Unsi 438
- 6 5555 6 439
- 0 0 1 1 0 0 441
- Branch On Coprocessor 0 False 442
- Branch On Coprocessor 0 True 445
- Opcode Table: 447
- 0 0 0 1 0 0 448
- 0 1 0 1 0 0 449
- 31 26 25 21 20 16 15 0 450
- 0 0 0 1 0 1 462
- 0 1 0 1 0 1 463
- 0 0 0 0 0 0 464
- 0 0 1 1 0 1 464
- Cache (1/4) 465
- Cache (2/4) 466
- Cache (3/4) 467
- Cache (4/4) 468
- 0 1 1 0 0 0 470
- 0 1 1 0 0 1 471
- 31 26 25 21 20 16 15 6 5 0 473
- 655 10 6 473
- Doubleword Divide Unsigned 474
- Divide Unsigned 476
- 6 5 555 6 488
- 31 26 25 24 6 5 0 495
- HIBERNATE 496
- 0 0 0 0 1 0 497
- 0 0 0 0 1 1 498
- Jump And Link Register 499
- Jump And Link Exchange 500
- 31 26 25 21 20 0 501
- 1 0 0 0 0 0 502
- 1 0 0 1 0 0 503
- 1 1 0 1 1 1 504
- Load Doubleword Left (1/3) 505
- Load Doubleword Left (2/3) 506
- Load Doubleword Left (3/3) 507
- Load Doubleword Right (1/3) 508
- Load Doubleword Right (2/3) 509
- Load Doubleword Right (3/3) 510
- 1 0 0 0 0 1 511
- 1 0 0 1 0 1 512
- 0 0 0 0 0 513
- 0 0 1 1 1 1 513
- 1 0 0 0 1 1 514
- Load Word Left (1/3) 515
- Load Word Left (2/3) 516
- Load Word Left (3/3) 517
- Load Word Right (1/3) 518
- Load Word Right (2/3) 519
- Load Word Right (3/3) 520
- Load Word Unsigned 521
- Multiply and Accumulate (1/5) 522
- Multiply and Accumulate (2/5) 523
- Multiply and Accumulate (3/5) 524
- Multiply and Accumulate (4/5) 525
- Multiply and Accumulate (5/5) 526
- 31 26 25 11 1016 15 0 528
- Move To Coprocessor0 530
- Move To HI 531
- Move To LO 532
- 31 26 25 21 20 6 5 0 533
- Or Immediate 537
- 1 0 1 0 0 0 538
- 1 1 1 1 1 1 539
- Store Doubleword Left (1/3) 540
- Store Doubleword Left (2/3) 541
- Store Doubleword Left (3/3) 542
- Store Doubleword Right (1/3) 543
- Store Doubleword Right (2/3) 544
- Store Doubleword Right (3/3) 545
- 1 0 1 0 0 1 546
- Shift Left Logical 547
- Shift Left Logical Variable 548
- 0 0 1 0 1 0 550
- 0 0 1 0 1 1 551
- 31 26 25 6 5 0 560
- 1 0 1 0 1 1 561
- Store Word Left (1/3) 562
- Store Word Left (2/3) 563
- Store Word Left (3/3) 564
- Store Word Right (1/3) 565
- Store Word Right (2/3) 566
- Store Word Right (3/3) 567
- 32, 64 T: SyncOperation ( ) 568
- System Call 569
- Trap If Equal 570
- Trap If Equal Immediate 571
- Probe TLB For Matching Entry 576
- Read Indexed TLB Entry 577
- Write Indexed TLB Entry 578
- Write Random TLB Entry 579
- Trap If Less Than Immediate 581
- Trap If Not Equal 584
- Trap If Not Equal Immediate 585
- 0 0 1 1 1 0 587
- APPENDIX B V 590
- Facsimile 595
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