Nec Network Controller uPD98502 Manual de usuario descargar pdf (Pagina 199)

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CHAPTER 3 SYSTEM CONTROLLER

Preliminary User’s Manual S15543EJ1V0UM

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3.2.12 S_PWCR (Power Control Register)

The power control register “S_PWCR” is a read-write and 32-bit word-aligned register. S_PWCR requests to keep

the idle state for USB Controller, Ethernet Controller, ATM Cell Processor, and PCI Controller by setting following

IDRQ fields. V

4120A must request these blocks to keep the idle state and check their acknowledgement by reading

the power status register “S_PWSR” prior to perform suspend by setting following STOP fields. S_PWCR is initialized

to 0 at reset and contains the following fields:

Bits Field R/W Default Description

31:22 Reserved R/W 0 Hardwired to 0.

21 PCISTOP R/W 0 Suspend request for PCI Controller:

0 = enable system clock for PCI Controller.

1 = disable system clock for PCI Controller.

20 Reserved R/W 0 Hardwired to 0.

19 MAC2STOP R/W 0 Suspend request for Ethernet Controller #2:

0 = enable system clock for Ethernet Controller #2.

1 = disable system clock for Ethernet Controller #2.

18 ATMSTOP R/W 0 Suspend request for ATM Cell Processor:

0 = enable system clock for ATM Cell Processor.

1 = disable system clock for ATM Cell Processor.

17 MACSTOP R/W 0 Suspend request for Ethernet Controller #1:

0 = enable system clock for Ethernet Controller #1.

1 = disable system clock for Ethernet Controller #1.

16 USBSTOP R/W 0 Suspend request for USB Controller:

0 = enable system clock for USB Controller.

1 = disable system clock for USB Controller.

15:6 Reserved R/W 0 Hardwired to 0.

5 PCIIDRQ R/W 0 Idle request for PCI Controller:

0 = do nothing.