Nec Network Controller uPD98502 Manual de usuario descargar pdf (Pagina 385)

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CHAPTER 7 PCI CONTROLLER

Preliminary User’s Manual S15543EJ1V0UM

385

7.3.4.2 Transition by power management event

The sequence is as follows:

1. When Power Management Event occurs, the V

4120A writes a ‘1’ to PMERQ bit in P_PPCR register.

2. The PCI Controller asserts PME_B if PME_En bit in PMCSR register is enabled.

3. An external PCI-Host device writes a ‘1’ to PME_Status bit in PMCSR register or writes a ‘0’ to PME_En bit in

PMCSR register in order to clear PME_B.

4. The PCI Controller deasserts PME_B.

Hereafter, as same case of the transition is issued by PCI-Host.

Figure 7-11. The Sequence of the Transition by PME

Same with the case that PCI-Host requests the transition of the power state

clear PME#

by writing '1' to PME_Status

bit in PMCSR register

or by making PME_En bit '0'

in PMCSR register disabled

assert PME#

if PME_En bit in PMCSR

deassert PME#

write '1' to PMERQ

in PPCR register

write

PCI-Host

PCI

Controller

Internal

Controller

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