NEC PD17062 Manual de usuario

The information in this document is subject to change without notice.DATA SHEETMOS INTEGRATED CIRCUITµPD17062Document No. IC-3560 (O.D. No. IC-8

10µPD1706223.5 PERIPHERAL HARDWARE REGISTER ... 28623.6 OTHERS

100µPD1706210.5.4 HSYNC Counter Data RegisterFig. 10.7 shows how the HSYNC counter data register functions .The HSYNC counter data register reads th

101µPD1706210.5.5 PWM Data RegisterFig. 10-8 shows how the PWM data register functions.The PWM data register sets the duty cycle of the 6-bit D/A co

102µPD1706210.5.6 Address RegistersThe address registers are mapped to addresses 74H to 77H in the system register (at data memory addresses74H to 7

103µPD1706210.5.7 PLL Data RegisterFig. 10-10 shows how the PLL data register functions.The PLL data register sets the frequency division ratio of t

104µPD1706210.6 PRECAUTIONS WHEN USING DATA BUFFERS10.6.1 Write Only, Read Only, and Unused Address Data Buffer PrecautionsWhen the 17K series ass

105µPD1706210.6.2 Peripheral Register Addresses and Reserved WordsWhen a 17K series assembler is used, no error is generated when peripheral address

106µPD1706211. INTERRUPTAn interrupt temporarily stops the program being executed in response to a request from the peripheralhardware (INTNC pin, t

107µPD17062Fig. 11-1 Interrupt Block Configuration3FH 2FHb3 b2 b1 b0 b3 b2 b1 b0IRQSIO0IRQVSYNIRQBTM0IRQNCIPSIO0IRVSYNIPBTM0IPNC01Hb3 b2 b1 b00SP2SP

108µPD1706211.2 INTERRUPT FUNCTIONThe following peripheral hardware can use the interrupt function: the INTNC pin, timer, VSYNC pin, and serialinte

109µPD1706211.2.4 Interrupt Permission Flags (IP×××)The interrupt permission flags set interrupt permissions for various types of peripheral hardwar

11µPD170621. PINS1.1 PIN FUNCTIONSPin No.DIP QFP(GC)SymbolDescription Output type At power-on resetP0C3|P0C0P0D3/ADC5|P0D0/ADC2PWM3|PWM0VDDVDD1VDD0

110µPD1706211.2.6 Interrupt Enable Flip-Flop (INTE)The interrupt enable flip-flop sets the interrupt permissions of all four types of interrupts.If

111µPD1706211.3 INTERRUPT ACCEPTANCE11.3.1 Interrupt Acceptance and PriorityAn interrupt is accepted as follows:(1) When the interrupt conditions

112µPD17062Fig. 11-2 Interrupt Acceptance FlowchartSTARTINTNC pin Timer VSYNC pin Serial interfaceIPNC=1? IPBTM0=1? IPVSYN=1? IPSIO0=1?NoYesNoYesNoY

113µPD1706211.3.2 Timing Chart at Interrupt AcceptanceFig. 11-3 shows the timing chart at interrupt acceptance.Fig. 11-3 (1) shows the timing chart

114µPD17062Fig. 11-3 Interrupt Reception Timing Chart (1/2)(1) When one interrupt (e.g., rising edge at the INTNC pin) is used(a) When an interrupt

115µPD17062Fig. 11-3 Interrupt Acceptance Timing Chart(2) When two or more interrupts (e.g., rising edge at the INTNC pin and falling edge at the VS

116µPD1706211.4 OPERATIONS AFTER INTERRUPT ACCEPTANCEWhen an interrupt is accepted, the following processing sequence is executed:(1) The interrupt

117µPD1706211.6 INTERRUPT PROCESSING ROUTINEAn interrupt is accepted in a program area that permits interrupts regardless of the program being execu

118µPD1706211.6.3 Notes on Interrupt Processing RoutineNote the following regarding the interrupt processing routine:(1) Data saved by hardwareAll b

119µPD17062Example Saving the status in an interrupt processing routineEIM046M047M048 M04D M04E M05F BTM0CK MEMMEMMEM MEM MEM MEMMEM 0.46H0.47H0.48H0.

12µPD17062Pin No.DIP QFP(GC)Symbol Description Output type At power-on resetP1A3|P1A0P1B3|P1B0REDGREENBLUEBLANKHSYNCVSYNCP1C3/ADC1P1C2P1C1ADC0P0B3/HSC

120µPD17062Fig. 11-4 Saving the System or Control Register Using the Window RegisterNumbers to correspond to the numbers in the program example.

121µPD1706211.7 EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN)There are two external interrupt sources: INTNC and VSYNC.An interrupt request is issued

122µPD1706211.7.2 FunctionsAn interrupt can be issued when either a rising or falling edge is input to the INTNC or VSYNC pin.Use the IEGNC or IEGVS

123µPD17062IEGNC or IEGVSYN flag change INTNC or VSYNC pin Whether interrupt IRQNC flagrequest is issued1 → 0 Low Not issued No change(F

124µPD1706211.9 MULTIPLE INTERRUPTSThe multiple interrupt function is used to process interrupt C or D while another interrupt from source Aor B is

125µPD1706211.9.1 Interrupt Source PrioritiesWhen using the multiple interrupt function, the priorities of interrupt sources must be determined.For

126µPD17062For multiple interrupts of more than two levels, operations of the device and emulator differ as shown inFigs. 11-8 and 11-9.At interrupt s

127µPD17062Fig. 11-7 Interrupt Stack Operation at Multiple Interrupts(a) Multiple level-2 interrupts(b) Multiple level-3 interruptsMAIN AMAINBAMAINR

128µPD17062MAIN AMAINBACBAMAINBAAARETIRETIRETAAAABANK0CLR1 IXEDIBANK0CLR1 IXEEIUndefinedUndefinedMain routine Interrupt A Interrupt B Interrupt CUndef

129µPD17062Fig. 11-9 Interrupt Stack Operation when 17K Series Emulator is UsedIf the RETI instruction is used on the emulator, the contents of the

13µPD17062Pin No.DIP QFP(GC)Symbol Description Output type At power-on resetINTNCNC48—55567810121422253739404142445657Interrupt input. Contains the n

130µPD1706211.9.3 Interrupt Level Restriction by Address Stack RegisterThe return address at control return from interrupt processing is automatical

131µPD1706211.9.4 Saving the Contents of System and Control RegistersThe contents of system and control registers must be saved before using the mul

132µPD17062In , specify the data memory bank containing the contents of the system register.Because the bank becomes BANK0 when an interrupt is accep

133µPD1706212. TIMERThe timer functions are used to manage the time in creating programs.12.1 TIMER CONFIGURATIONFig. 12-1 shows the configuration

134µPD1706212.2 TIMER FUNCTIONSThere are two timer functions, timer carry FF check and timer interrupt.The timer carry FF check function performs ti

135µPD17062Fig. 12-2 Relationship Between the Timer Mode Select Register and Timer Interval Set Pulseb3 b2 b1 b0 BTM0ZXBTM0CK2BTM0CK1BTM0CK009HR/WR

136µPD1706212.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF)The timer carry FF is set to 1 by the positive-going edge of the timer carry FF set pulse spec

137µPD1706212.3.1 Example of Using the Timer Based on the BTM0CY FlagAn example of a program follows.Example INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT B

138µPD1706212.3.2 Timer Error Caused by the BTM0CY FlagThere are two types of timer error that can occur because of the BTM0CY flag. One type depen

139µPD17062(2) Timer error that occurs when the timer carry FF setting time interval is changedThe timer carry FF setting time interval is specified

14µPD170621.2 EQUIVALENT CIRCUITS OF THE PINSP0A (P0A3/SO, P0A2/SCK)P0B (P0B1, P0B0/SI)P1B (P1B3, P1B2, P1B1, P1B0)P1C (P1C3/ADC1, P1C2, P1C1)VDDVDD

140µPD17062As shown in Fig. 12-5, if the timer carry FF setting time interval is switched, the timer error that occurs beforethe BTM0CY flag is set fo

141µPD1706212.4 CAUTIONS IN USING THE TIMER CARRY FFThe timer carry FF is used not only as a timer function but also as a reset sync signal at a CE

142µPD1706212.4.1 Timer Update Time and BTM0CY Flag Check Time IntervalAs described in Section 12.3.1, the time interval tSET at which the BTM0CY fl

143µPD1706212.4.2 Correcting the Timer Carry FF at a CE resetThis section describes an example of correcting the timer at a CE reset.If the timer ca

144µPD17062Fig. 12-6 Timing ChartAs shown in Fig. 12-6, the positive-going edge of the internal 10 Hz pulse starts the program at 000H ata power-on

145µPD1706212.4.3 If the BTM0CY flag is checked at the same time with a CE resetAs described in Section 12.4.2, a CE reset occurs at the same time t

146µPD17062The program shown below is an example of a program that meets the above condition. Do not createssuch a program.ExampleProcess AINITFLG

147µPD1706212.5 TIMER INTERRUPTThe timer interrupt function issues an interrupt request at the negative-going edge of the timer interruptpulse speci

148µPD1706212.5.1 Example of Using a Timer Based on a Timer InterruptAn example follows.ExampleBR AAA ; Branches to AAA.TIMER: ; Program address 000

149µPD1706212.5.2 Timer Interrupt ErrorAs explained in Section 12.4, an interrupt request is accepted each time the timer interrupt pulse goes low,p

15µPD17062P0C (P0C3, P0C2, P0C1, P0C0)RED, GREEN, BLUE, BLANK, PSC(Output)PWM (PWM3, PWM2, PWM1, PWM0)P1A (P1A3, P1A2, P1A1, P1A0)(Output)P0D (P0D3/AD

150µPD17062Fig. 12-9 Timer Interrupt Error (2/2)(b) When the timer interrupt pulse is switchedEI EI EI EIIRQBTM0IPBTM0INTEFF EIDIInternal pulse

151µPD1706212.6 CAUTIONS IN USING THE TIMER INTERRUPTIn a program using a timer that operates at constant intervals once a power-on reset occurs, it

152µPD17062In reality, however, to avoid skipping the timer process in the above example, a delay is provided betweenthe negative-going edge of the ti

153µPD1706213. STANDBYThe standby function is intended to reduce the current drain of the device at backup.13.1 STANDBY BLOCK CONFIGURATIONFig. 13-

154µPD1706213.2 STANDBY FUNCTIONThe standby function stops the whole or part of the operation of the device to reduce its current drain.The standby

155µPD1706213.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PINThe CE pin controls the following items according to the level and positive-going edge

156µPD1706213.4 HALT FUNCTIONThe halt function stops the operation of the CPU clock by executing the HALT h instruction.When the HALT h instruction

157µPD1706213.4.2 Halt Release ConditionsFig. 13-3 summarizes the release conditions.As shown in Fig. 13-3, the halt release condition is 4-bit data

158µPD1706213.4.3 Halt Release by Key EntryThe HALT 0001B instruction specifies a key entry as a halt release condition.If this condition is specifi

159µPD17062(2) Cautions in using the P0D0/ADC2 to P0D3/ADC5 pins for an A/D converterP0D3/ADC5P0D2/ADC4P0D1/ADC3P0D0/ADC2A/D inputA/D inputLatchGenera

16µPD17062P0B3/HSCNTPortHorizontal synchronizingsignal counterP-chN-chP0B2/TMINPortTimer/counterP-chN-ch

160µPD17062(3) Alternative method to release the halt stateP0D3/ADC5P0D2/ADC4P0D1/ADC3P0D0/ADC2Output portLatchMicroprocessor or the likeGeneral-purpo

161µPD1706213.4.4 Releasing the Halt State by the Timer Carry FFThe HALT 0010B instruction specifies the timer carry FF as a halt release condition.

162µPD1706213.4.5 Releasing the Halt State by an InterruptThe HALT 1000B instruction specifies an interrupt as halt release condition.If it is speci

163µPD17062ExampleHLTINT DAT 1000B ; Defines a symbol.START: ; Address 0000HBR MAIN ;NOPINTTM: ; Timer interrupt vector address (0003H)BR INTTIMER ; B

164µPD1706213.5 CLOCK STOP FUNCTIONThe clock stop function stops the operation of the 8 MHz crystal oscillator by executing the STOP sinstruction.Th

165µPD17062Fig. 13-4 Releasing the Clock Stop State by a CE ResetFig. 13-5 Releasing the Clock Stop State by a Power-on Reset5 V0 VVDDCE pinCrysta

166µPD1706213.5.3 Cautions in Using the Clock Stop InstructionThe clock stop instruction (STOP s) is effective only when the CE pin is at a low leve

167µPD1706213.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP13.6.1 State of Each Pin at a Halt and Clock StopTable 13-1 summarizes how the CPU

168µPD17062Stops at the addressof the HALTinstruction.Holds the previousstate.Holds the previousstate.Holds the previousstate.Operates normally.Operat

169µPD1706213.6.2 Cautions in Processing of Each Pin During Halt or Clock Stop StateThe halt function is intended to reduce the required current dra

17µPD17062HSYNC, VSYNC, INTNC, CE(Hysteresis input)XOUT, XINXINXOUTEOVCO(Input)

170µPD17062Table 13-2 State of Each Pin During the Halt or Clock Stop State and Cautions to Be Taken (2/2)INTNCREDGREENBLUEBLANKHSYNCVSYNCPWM3PWM2PW

171µPD1706214. RESETThe reset function is used to initialize device operation.14.1 RESET BLOCK CONFIGURATIONFig. 14-1 shows the configuration of th

172µPD1706214.2 RESET FUNCTIONPower-on reset is applied when VDD rises from a certain voltage, CE reset is applied when the CE pin risesfrom low lev

173µPD1706214.3 CE RESETCE reset is executed by raising the CE pin from low level to high level.When the CE pin rises to high level, the RESET signa

174µPD1706214.3.2 CE Reset When Clock-Stop (STOP Instruction) UsedFig. 14-3 shows the reset operation.When clock-stop is used, the IRES, RES and RES

175µPD1706214.3.3 Cautions at CE ResetWhen CE reset is used, careful attention must be given to points (1) and (2) below regardless of theinstructio

176µPD17062Example 2.; SKT1 FLG1 ; If FLG1 is set to 1,BR LCTUNEST M1, R1 ; data is rewritten to M1 and M2 again.ST M2, R2CLR1 FLG1; LCTUNE :Initial r

177µPD1706214.4 POWER-ON RESETPower-on reset is executed by raising VDD from a certain voltage (called the power-on clear voltage) or less.When VDD

178µPD1706214.4.1 Power-on Reset at Normal OperationFig. 14-5 (a) shows power-on reset at normal operation.As shown in Fig. 14-5 (a), when the VDD d

179µPD17062Fig. 14-5 Power-on Reset and VDD(a) During normal operation (including halt state)(b) At clock-stop(c) When VDD rises from 0 V5 V0 V“H”No

18µPD170622. PROGRAM MEMORY (ROM)Program memory stores the program to be executed by the CPU, as well as predetermined constant data.2.1 CONFIGURAT

180µPD1706214.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESETWhen supply voltage is first turned on, power-on reset and CE reset may be applied s

181µPD17062Fig. 14-6 Relationship Between Power-on Reset and CE Reset(a) When VDD and CE pin raised simultaneously(b) When CE pin raised in halt st

182µPD1706214.5.4 Cautions When Supply Voltage RaisedWhen supply voltage is raised, careful attention must be given to points (1) and (2) below.(1)

183µPD17062(2) At return from clock-stop stateWhen returning from the back-up state when clock-stop is used to back-up supply voltage at 2.2 V, VDDmus

184µPD1706214.6 POWER FAILURE DETECTIONPower failure detection is used to judge whether the device is reset by turning on VDD or by the CE pin, assh

185µPD17062Fig. 14-10 BTM0CY Flag State TransitionVDD = L→3.5 VCE = L CE = HCE = H→LSTOP 0BTM0CY = 0CE = L→HCE = L→HCE = H→LCE = L→HCE = L→HSTOP 0BT

186µPD17062Fig. 14-11 BTM0CY Flag Operation(a) When BTM0CY flag not detected even once (neither SKT1 BTM0CY nor SKF1 BTM0CY executed)(b) When power

187µPD1706214.6.2 Cautions at Power Failure Detection with BTM0CY FlagWhen clock counting, etc. is performed with the BTM0CY flag, careful attention

188µPD17062ExampleSample programSTART: ; Program address 0000H; Reset processing ;; SKT1 BTM0CY ; Power failure detectionBR INITIALBACKUP:; Clock upda

189µPD1706215. GENERAL-PURPOSE PORTA general-purpose port outputs a high level, low level, or floating signal to an external circuit and readsa high

19µPD170622.2 FUNCTIONS OF PROGRAM MEMORYProgram memory has two basic functions:(1) Program storage(2) Constant data storageA program is a set of

190µPD17062Table 15-1 Classification of General-Purpose PortsGeneral-purpose portsClassification of general-purpose ports Target ports Data setting

191µPD17062b3 b2 b1 b0mnPPPP3210Weight of port register bitPort register address (Examples: 70H = A, 71H = B, 72H = C, 73H = D)Port register bank&quo

192µPD1706215.2.2 General-Purpose I/O Ports (P0A, P0B, P1B, P1C)The I/O of P0A is switched by the P0A bit I/O selection register (RF address 37H).

193µPD17062Table 15-2 Relationship between Each Port (Pin) and Port RegisterNote Nothing is mapped to b0 of 72H. When b0 is read, 0 is always read.

194µPD1706215.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C)15.3.1 Configuration of I/O PortsIn the following, (1) to (3) explain the configurat

195µPD1706215.3.3 Port0A Bit I/O Selection Register (P0ABIO)Port0B Bit I/O Selection Register (P0BBIO)Port1B Bit I/O Selection Register (P1BBIO)Port1C

196µPD1706215.3.4 To Use an I/O Port (P0A, P0B, P1B, P1C) as an Input PortSelect the pin to be used as an input port by using the I/O selection regi

197µPD1706215.3.6 Notes on Using I/O Ports (P0A1 and P0A0)As shown in the example below, when pins P0A1 and P0A0 pins are used as output pins, the c

198µPD1706215.4 GENERAL-PURPOSE INPUT PORT (P0D)15.4.1 ConfigurationThe following explains the configuration of the input port.(1) P0D (P0D3, P0D2

199µPD1706215.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A)15.5.1 Configuration of Output Ports (P0C, P1A)(1) and (2), below, show the configuration o

2µPD17062ORDERING INFORMATIONPart number PackageµPD17062CU-××× 48-pin plastic shrink DIP (600 mil)µPD17062GC-××× 64-pin plastic QFP (14 × 14 mm)Remark

20µPD170622.4 BRANCHING A PROGRAMA program is branched by execution of the branch instruction (BR).Fig. 2-2 illustrates the operation of the branch

200µPD1706215.5.2 Example of Using Output Ports (P0C, P1A)The output ports output the contents of the output latch from each pin.Output data can be

201µPD1706216. SERIAL INTERFACEThe µPD17062 has two sets of serial interface pins, channel 0 (CH0) and channel 1 (CH1), for exchangingdata with an ex

202µPD17062Table 16-2 CH0 Operation ModesRemark × : Don’t careSerial interface Port 0A I/OSDA pin SCL pin Operation modemode register specification

203µPD17062Table 16-3 CH1 Operation ModesRemark ×: Don’t careSerial interface Port 0A I/OSI pin SCK pin SO pin Operation modemode register specific

204µPD1706216.1.1 SIO0CHThe SIO0CH flag is used to select the channel of the serial interface.When the SIO0CH flag is set to 0, the serial interface

205µPD1706216.1.3 SIO0MSThe SIO0MS flag specifies the serial interface clock to be used.When the SIO0MS flag is set to 0, the external clock is sele

206µPD1706216.2 CLOCK COUNTERThe clock counter is a wrap around counter that counts the clock of the shift clock pin (P0A1/SCL pin forCH0, P0A2/SCK

207µPD1706216.3 STATUS REGISTERThe status register is a four-bit read-only register that retains the start and stop states in two-wire bus modeand t

208µPD1706216.3.4 SIO0SF8 (Serial I/O Shift 8 Clock) FlagThe SIO0SF8 flag, mapped to b3 of the status register, is set to 1 when the contents of the

209µPD1706216.4 WAIT REGISTERThe µPD17062 can set a state in which the serial interface hardware does not operate, even if a shift clockis input. T

21µPD17062Fig. 2-2 Operation of Branch Instruction and Machine Code(a) Direct branch (BR addr) (b) Indirect branch (BR @AR)Address Program memoryL

210µPD17062Table 16-8 Wait Timings(1) Slave operation wait in two-wire bus modeWhen the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the SCL pi

211µPD17062(2) Master operation wait in two-wire bus modeMaster operation wait in two-wire bus mode incurs the interruption of transmission. In this

212µPD1706216.4.2 SIO0NWT (Serial I/O No-Wait) FlagWriting appropriate data into the SIO0NWT flag can both release wait and execute forced wait.(1)

213µPD17062(2) For transmission in two-wire bus mode (SIO0TX = 1)In this case, the contents of an acknowledgement received from the receiver side are

214µPD1706216.5 PRESETTABLE SHIFT REGISTER (PSR)The presettable shift register is an 8-bit register. It outputs the contents of the most significan

215µPD1706216.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD)The interrupt source register (SIO0IMD) is a four-bit register that specifies whe

216µPD17062Bit position b3 b2 b1 b0Flag name SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0(0) (0)SIO0CK1 SIO0CK0 Internal clock frequency0 0 100 kHz0 1 200 kHz1 0

217µPD17062Peripheral equipment Peripheral address Corresponding pinPWM0 05H PWM0PWM1 06H PWM1PWM2 07H PWM2PWM3 08H PWM317. D/A CONVERTER17.1 PWM P

218µPD17062Fig. 17-1 PWMR Structure and the Corresponding DBF BitsFig. 17-2 Waveform Output from the PWM Pinb3 b2 b1 b0 b3 b2 b1 b0b6 b5 b4 b3 b2

219µPD1706218. PLL FREQUENCY SYNTHESIZER18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATIONFig. 18-1 is a block diagram of the PLL frequency synthesizer.A

22µPD170622.5 SUBROUTINEIf a subroutine is executed, the specialized subroutine call instruction (CALL) and subroutine returninstruction (RET, RETSK

220µPD1706218.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCKThe PLL frequency synthesizer receives an input signal at the VCO pin, divides its f

221µPD1706218.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER18.3.1 Programmable Divider ConfigurationFig. 18-2 shows the configuration o

222µPD1706218.3.2 Programmable Divider (PD) and Data Buffer (DBF)The programmable divider divides the frequency of an input signal at the VCO pin by

223µPD1706218.4 REFERENCE FREQUENCY GENERATOR (RFG)18.4.1 Reference Frequency Generator (RFG) Configuration and FunctionsFig. 18-3 shows the confi

224µPD1706218.4.2 PLL Reference Mode Select Register Configuration and FunctionsFig. 18-4 shows the configuration and functions of the PLL reference

225µPD1706218.5 PHASE COMPARATOR (φ-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK18.5.1 Configuration of the Phase Comparator (φ-DET), Charge Pump

226µPD1706218.5.2 Functions of the Phase Comparator (φ-DET)As shown in Fig. 18-5, the phase comparator compares the phase of the output frequency “f

227µPD17062Fig. 18-6 Relationship among fr, fN, UP, and DW Signals(1) When fN is lagging behind fr(2) When fN is leading fr(3) When fN is in phase w

228µPD1706218.5.3 Charge PumpAs shown in Fig. 18-5, the charge pump directs the up request signal (UP) or down request signal (DW)from the phase com

229µPD17062(1) PLL unlock FF judge register (PLLULJDG)This register is a read-only register. It is reset when its content is read into a window regis

23µPD17062Fig. 2-3 Operation of Subroutine Call Instruction(a) Direct subroutine call (CALL addr) (b) Indirect subroutine call (CALL @AR)Address P

230µPD17062(2) PLL unlock FF delay control register (PLULSEN)When the unlock FF disable mode is selected, the unlock FF remains set. So, note that if

231µPD1706218.6 PLL DISABLE MODEThe PLL frequency synthesizer is disabled when the CE pin is at a low level. It is also disabled when thePLL refere

232µPD17062PLLR0000 0110 1100 111106 CFPLRFMODE00106.25 kHz18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZERThe following data is necessary to con

233µPD1706219. A/D CONVERTERThe µPD17062 contains a 4-bit program-controlled A/D converter that operates with a successive compari-son method.19.1

234µPD1706219.2 D/A CONVERTER CONFIGURATIONThe D/A converter used in the A/D converter of the µPD17062 is a resistor string D/A converter consisting

235µPD1706219.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR)The ADCR is a 4-bit register to specify a reference voltage for the A/D converter. It is m

236µPD17062b3b2b1#0(MSB) (LSB)(RF : 21H)ADCCMPADCCH2 ADCCH1 ADCCH0 Selected pin0 0 0 ADC00 0 1 P1C3/ADC10 1 0 P0D0/ADC20 1 1 P0D1/ADC31 0 0 P0D2/ADC41

237µPD1706219.6 EXAMPLE OF A/D CONVERSION PROGRAMThe following example shows an A/D conversion program based on the successive comparison method.The

238µPD17062FlowchartSTARTDBF←1000BADCR←DBFADCCMPDBF0B3←0DBF0B2←1ADCR←DBFADCCMP1010DBF0B2←0DBF0B1←11Sets DBF data.Begins AD conversion.Judges compariso

239µPD17062ENDADCR←DBFADCCMPDBF0B1←0DBF0B0←1ADCR←DBFADCCMP1010DBF0B0←0 DBF0B0←0DBF0B1←0DBF0B0←11Sets reference voltage.Judges comparison result.Sets r

24µPD170622.6 TABLE REFERENCEThe table reference instruction is used to reference the constant data in program memory. If the MOVTDBF, @AR instructi

240µPD17062TV screen19 characters14 rows20. IMAGE DISPLAY CONTROLLERThe image display controller (IDC) function indicates a channel number, volume of

241µPD17062(4) Rounding, rimming, and reverse video can be specified for individual characters.(5) Number of fonts: 120 (user-programmable)The number

242µPD17062(6) Up to 4 different character sizes, both vertical and horizontal, are available.The same vertical character size is specified for all ch

243µPD1706220.2 DIRECT MEMORY ACCESSThe direct memory access (DMA) function transfers memory contents directly to peripheral equipment,without using

244µPD17062Sample programRemark The “SET1” or “CLR1” is not included in the µPD17062 instruction set. They are a built-in macroinstruction of the 17K

245µPD17062b3 b2 b1 b00 0 IDCEN010Turns off the display.Turns on the display.(RF 31H)------------20.3 IDC ENABLE FLAGThe IDCEN (IDC enable) flag is

246µPD1706220.4 VRAMVRAM is the memory that holds data used to select a picture pattern that the IDC displays on a screen suchas a TV screen. In th

247µPD17062Fig. 20-2 VRAM Data Configuration20.4.1 ID FieldThe ID field indicates the type of data in the data field.The data field can hold the f

248µPD17062Table 20-4 VRAM Data (Character Pattern Select Data) versus CROM AddressesVRAM dataCROM addressVRAM dataCROM address(8 bits)BANK0 BANK1(8

249µPD17062Sample programIf the CROM data and VRAM data are specified as shown above, the display on the screen varies dependingon the CROM bank.The C

25µPD170623. PROGRAM COUNTER (PC)The program counter addresses program memory or a program. It is a 12-bit binary counter.Fig. 3-1 Program Counte

250µPD1706220.4.3 Carriage Return DataThe term carriage return data refers to the data pointing to the address of the VRAM data that specifiesthe fi

251µPD17062Fig. 20-4 Carriage Return Data (8 Bits Including the ID Field)01234567 89ABCDEF40 41 42 43 44 45 46 47048 49 4A 4B 4C 4D 4E 4F150 51 52 5

252µPD1706220.4.4 Control Data Select DataThe term control data refers to the data that specifies the character size, display position, and color of

253µPD17062Table 20-5 VRAM Data (Control Data Select Data) versus CROM AddressesVRAM dataCROM addressVRAM dataCROM address(8 bits)BANK0 BANK1(8 bits

254µPD1706220.4.5 Cautions in Specifying VRAM Data(1) Reset the IDCEN flag to 0 before specifying VRAM data.(2) The VRAM data must begin at 00H in B

255µPD1706220.5 CHARACTER ROMThe CROM (character ROM) consists of the IDC pattern data and control data. The CROM data shares theprogram memory wit

256µPD17062Fig. 20-6 Character Pattern Data Configuration(a) Data for a character with no rimming(b) Data for a character with rimmingIf 2 is to be

257µPD17062Fig. 20-8 Example of the Pattern of a Character with Rimming××××0H××××1H××××2H××××3H××××4H××××5H××××6H××××7H××××8H××××9H××××AH××××BH××××C

258µPD1706220.5.2 Control DataThe control data specifies the display position, size, and color of a character pattern. It is stored at ×××FHin the

259µPD17062(2) Vertical size data (b12 and b11 of the control data)The vertical size data determines the vertical size of each image of a character.

26µPD170624. STACKThe stack is a register used to save an address returned by a program or the contents of the system register,described later, when

260µPD17062(4) Vertical position data (b6 to b3 of the control data)The vertical position data specifies which of the 12 rows (vertical positions) sho

261µPD17062(5) Color data (b2 to b0 of the control data)The color data specifies the color of a display character. It is output from a specified outp

262µPD1706220.5.3 Defining Display Patterns with an AssemblerWith the 17K series assembler, the DCP pseudo instruction can be used to define display

263µPD1706220.6 BLANK, R, G, AND B PINSAll these pins are CMOS push-pull output pins. They output an active-high signal. The BLANK pin outputsa si

264µPD1706220.7 SPECIFYING THE DISPLAY START POSITIONIDC display start positions (upper left of the screen) can be specified by setting data in the

265µPD1706220.7.1 Horizontal Start Position Setting RegisterIf the horizontal start position setting register contains 0H, the horizontal start posi

266µPD1706220.7.2 Vertical Start Position Setting RegisterIf the vertical start position setting register contains 0H, the vertical start position i

267µPD17062The vertical start position of the display character is determined by the vertical start position register. Atthis point, the vertical sta

268µPD1706220.8 SAMPLE PROGRAMSThe following sample program generates a display shown below.The RAM names of VRAM are defined as follows (tentative)

269µPD17062The sample program follows:Program start; Performs initialization such as clearing RAM. InitializationSET1 IDCDMAEN ; Selects the DMA

27µPD170624.3 ADDRESS STACK REGISTERS (ASRs)There are six address stack registers, each consisting of 13 bits. After a subroutine call instruction

270µPD17062At point , the contents of VRAM (BANK2) are as follows:For this example, the contents of CROM are as follows:0810203C405D68718090A0B2C4D0E

271µPD17062; ********;********;********10810 00000811 00060812 000E0813 001E0814 00760815 00C60816 01860817 00060818 00060819 0006081A 0006081B 000608

272µPD17062; ********;********;********30830 00000831 007C0832 00FE0833 01C70834 01830835 0003DCP 0, 'DCP 0, ' DCP 0, ' DCP 0, &apo

273µPD17062; ********;********;********H08D0 000008D1 018308D2 018308D3 018308D4 018308D5 018308D6 018308D7 01FF08D8 01FF08D9 018308DA 018308DB 018308

274µPD1706221. HORIZONTAL SYNC SIGNAL COUNTER21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATIONThe horizontal sync signal counter counts the frequen

275µPD1706221.2 GATE CONTROL REGISTER (HSCGT)The gate control register is a 2-bit register consisting of the HSCGT1 and HSCGT0 flags used to control

276µPD1706221.3 HSYNC COUNTER (HSC)The HSYNC counter is mapped at peripheral address 04H. It is a 6-bit read-only binary counter. It can beread-ac

277µPD1706222. INSTRUCTION SETS22.1 OUTLINE OF INSTRUCTION SETS b15b14-b11 0 1BIN HEX0 0 0 0 0 ADD r, m ADD m, #n40 0 0 1 1 SUB r, m SUB m,

278µPD1706222.2 INSTRUCTIONSLegendAR : Address registerASR : Address stack register pointed to by the stack pointeraddr : Program memory address (11

279µPD1706222.3 LIST OF INSTRUCTION SETSInstructionsetAddSubtractLogicaloperationTestCompareRotationTransferMne-monicADDADDCINCSUBSUBCORANDXORSKTSKF

28µPD17062Fig. 4-3 Structure of Interrupt Stack RegistersMSB LSB0H1HBANKSK0BANKSK1IXESK0IXESK1Fig. 4-4 Behavior of Interrupt Stack RegistersNot d

280µPD17062Instruction codeMne-monicPUSHPOPPEEKPOKEGETPUTBRCALLRETRETSKRETIEIDISTOPHALTNOPOperandARARWR, rfrf, WRDBF, pp, DBFaddr@ARaddr@ARshInstructi

281µPD1706222.4 BUILT-IN MACRO INSTRUCTIONSThe following macro instructions are built in the 17K series assembler (AS17K). For details, refer to th

282µPD1706223. RESERVED SYMBOLS FOR ASSEMBLERThe reserved µPD17062 symbols for the assembler are listed below.23.1 SYSTEM REGISTERMEMMEMMEMMEMMEMME

283µPD1706223.3 PORT REGISTERSymbol Attribute ValueRead/ DescriptionwriteP0A3 FLG 0.70H.3 R/W Bit 3 of port 0AP0A2 FLG 0.70H.2 R/W Bit 2 of po

284µPD17062Symbol Attribute ValueRead/ DescriptionwriteIDCDMAEN FLG 0.80H.1 R/W DMA enable flagSP MEM 0.81H R/W Stack pointerCE FLG 0.8

285µPD17062Symbol Attribute ValueRead/ DescriptionwriteSIO0SF8 FLG 0.0A8H.3 R SIO0 shift 8 clock flagSIO0SF9 FLG 0.0A8H.2 R SIO0 shift 9 cloc

286µPD1706223.5 PERIPHERAL HARDWARE REGISTERSymbol Attribute ValueRead/ DescriptionwriteIDCORG DAT 01H R/W IDC start position setting regi

287µPD1706224. ELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGS (Ta = 25 ±2 °C)Parameter Symbol Rated value UnitSupply voltage VDD –0.3 to +6.0 VIn

288µPD17062AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ±10 %, RH ≤ 70 %)Parameter Symbol Conditions Min. Typ. Max. UnitOperating frequency fin1

289µPD1706225. PACKAGE DRAWINGS48PIN PLASTIC SHRINK DIP (600 mil)ITEM MILLIMETERS INCHESNOTES1) Each lead centerline is located within 0.17 mm (0.0

29µPD170625. DATA MEMORY (RAM)Data memory is used to store data for operations and control. Simply by executing an appropriateinstruction, data can

290µPD1706264 PIN PLASTIC QFP ( 14)ITEM MILLIMETERS INCHESFGKNJ1.01.6±0.20.100.8 (T.P.)1.0Q0.0390.0390.063±0.0080.0040.031 (T.P.)S64GC-80-3BE-1ACNO

291µPD1706226. RECOMMENDED SOLDERING CONDITIONSThe conditions listed below shall be met when soldering the µPD17062.For details of the recommended

292µPD17062Name DescriptionAPPENDIX DEVELOPMENT TOOLSThe following support tools are available for developing programs for the µPD17062.HardwareThe I

293µPD1706217K seriesassembler(AS17K)Device file(AS17062)Support software(SIMPLEHOST)µS5A10AS17KµS5A13AS17KµS7B10AS17KµS7B13AS17KµS5A10AS17062µS5A13AS

294µPD17062[MEMO]

295µPD17062Cautions on CMOS DevicesCountermeasures against static electricity for all MOSsCaution When handling MOS devices, take care so that they ar

296µPD17062SIMPLEHOST is a trademark of NEC Corporation.MS-DOS and Windows are trademarks of Microsoft Corporation.PC/AT and PC DOS are trademarks of

3µPD17062PIN CONFIGURATION (TOP VIEW)48-pin plastic shrink DIP (600 mil)ADC0 to ADC5 : A/D converter input P0D0 to P0D3 : Port 0DBLANK : Blanking si

30µPD17062Fig. 5-1 Data Memory Structure0123456789ABCDEF01234567DBF3 DBF2 DBF1 DBF0P0A (4 bits)System registerP0B (4 bits)P0C (4 bits)P0D (4 bits)BA

31µPD170625.1.1 Structure of the System Register (SYSREG)The system register consists of 12 nibbles, located at addresses 74H to 7FH in data memory.

32µPD170625.1.3 Structure of the General-Purpose Register (GR)The general-purpose register consists of 12 nibbles, specified with an arbitrary row a

33µPD170625.1.4 Structure of Port Data Registers (port register)The port registers consist of 12 nibbles at addresses 70H to 73H of the banks of dat

34µPD170625.2 FUNCTIONS OF DATA MEMORYData memory can be used to perform, with one instruction, a four-bit operation, comparison, decision, ortransf

35µPD170625.2.1 Function of System Register (SYSREG)The system register is used to control the CPU.For example, the bank register shown in Fig. 5-2

36µPD17062Table 5-1 Data Memory Manipulation InstructionsFunction InstructionADDADDCSUBSUBCANDORXORSKESKGESKLTSKNEMOVLDSTSKTSKFAdditionSubtractionLo

37µPD17062Fig. 5-6 Correspondence Between Port Registers and Ports (Pins)70H P0A71H P0B72H P0C73H P0D70H P1A71H P1B72H P1C73H Fixed at 0b3 P0A3b2 P0

38µPD170625.3 NOTES ON USING DATA MEMORY5.3.1 Addressing Data MemoryIf the 17K series assembler is being used and a numeric representing a data me

39µPD17062Example 2.5.3.2 Notes on Using Unmounted Data MemoryAs shown in Fig. 5-6, nothing is actually assigned to bit 0 (LSB) of address 72H of BA

4µPD1706264-pin plastic QFP (14 × 14 mm)1324657981012111315141617 18 19 20 21 22 23 24 25 26 27 28 29 30 31 324846474543444240413937383634353364 63 62

40µPD170626. GENERAL-PURPOSE REGISTER (GR)The general-purpose register is allocated in data memory space, and is used to perform direct operationson

41µPD17062Fig. 6-1 Structure of General-Purpose RegisterRPH RPL7DH 7EHb3 b2 b1 b0 b3 b2 b1 b00000b2b1b0 BCD(RP)0123456789ABCDEF023456710234567102345

42µPD170626.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUALINSTRUCTIONSTable 6-1 lists the operation and transfer inst

43µPD17062Example 1. When BANK0 is selectedAND RPL, #0001B ; RP ← 0000000B; The general-purpose register is allocated in row; address 0H in BANK0.ADD

44µPD17062Example 2. When BANK0 is selected and MPE = 0 is specifiedMOV 04H, #8 ; 04H ← 8AND RPL, #0001B ; RP ← 0000000B; The general-purpose regis

45µPD17062Example 3 shows a program that transfers eight words of data from BANK2 to BANK0 data memory in unitsof four words, as shown in Fig. 6-4. I

46µPD170626.4 NOTES ON USING THE GENERAL-PURPOSE REGISTERThis section provides notes on using the general-purpose register, referring to the followin

47µPD17062Fig. 6-5 Execution of the Above ExampleAlso, note the following when the general-purpose register is being used. No arithmetic/logical in

48µPD170627. ARITHMETIC LOGIC UNIT (ALU) BLOCK7.1 OVERVIEWFig. 7-1 is an overview of the ALU block.As shown in Fig. 7-1, the ALU block consists of

49µPD170627.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK7.2.1 ALUIn response to a programmed instruction, the ALU performs 4-b

5µPD17062BLOCK DIAGRAMVCOPSCEOHSYNCVSYNCREDGREENBLUEBLANKP0A0/SDAP0A1/SCLP0A2/SCKP0A3/SOP0B0/SIP0B1P0B2/TMINP0B3/HSCNTP0D0/ADC2P0D1/ADC3P0D2/ADC4P0D3/

50µPD17062Table 7-1 ALU OperationsALU functionAdditionSubtractionLogic operationDiscrimi-nationComparisonTransferRotationADDADDCSUBSUBCORANDXORSKTSK

51µPD17062Table 7-2 Modification of the Data Memory Address and Indirect Transfer Address by the Index Registerand Data Memory Row Address PointerBANK

52µPD17062Table 7-3 Converted Decimal DataRemark Correct decimal conversion is not possible in the shaded area.OperationresultHexadecimal addi-tion0

53µPD170627.4 NOTES ON USING THE ALU7.4.1 Notes on Using the Program Status Word for OperationsAfter an arithmetic operation has been performed on

54µPD170628. SYSTEM REGISTER (SYSREG)“System register” is the generic name for those registers directly related to CPU control. System registersare

55µPD17062b30b20b10b00b30b20b10b00b3 b2 b1 b0 b3 b2 b1 b0AR15 (MSB) AR0 (LSB)AR0(77H)AR1(76H)AR2(75H)AR3(74H)8.1 ADDRESS REGISTER (AR)The addres

56µPD170628.3 BANK REGISTER (BANK)The bank register specifies a data memory bank.The bank register contains BANK0 upon reset. The two high-order bi

57µPD170628.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP)8.5.1 Configuration of Index Register and Data Memory Row Address Pointe

58µPD170628.5.2 Functions of Index Register and Data Memory Row Address PointerWhen a data memory manipulation instruction is executed with the inde

59µPD17062Table 8-2 Modification of Data Memory Address by Index Register andData Memory Row Address Pointer M ; Data memory address BANK ; Bank regi

6µPD17062CONTENTS1. PINS ...

60µPD170628.5.3 For MPE = 0 and IXE = 0 (Data Memory Not Modified)As shown in Table 8-2, data memory addresses are not affected by the index registe

61µPD17062Fig. 8-3 Indirect Transfer of General-Purpose Register with MPE = 0 and IXE = 0Address generation of example 2RM000033548(@ r)@ r, mMOV05H

62µPD170628.5.4 For MPE = 1 and IXE = 0 (Diagonal Indirect Transfer)As shown in Table 8-2, the bank and row address of the data memory address in th

63µPD17062Fig. 8-4 Indirect Transfer of General-Purpose Register with MPE = 1 and IXE = 0Address generation of example 1RM000 0 0 0031 0 1548(@ r)@

64µPD170628.5.5 For MPE = 0 and IXE = 1 (Index Modification)As shown in Table 8-2, when a data memory manipulation instruction is executed, the bank

65µPD17062Fig. 8-5 Data Memory Address Modification with IXE = 101 2 3 45 6R01234MADD r, mColumn addressRow addressGeneral-purposeregisterSpecifiedb

66µPD170628.6 GENERAL-PURPOSE REGISTER POINTER (RP)The general-purpose register pointer points to the bank and row address of the general-purpose re

67µPD170629. REGISTER FILE (RF)The register file is a group of registers that mainly control the CPU peripheral circuits. The register file hasa cap

68µPD17062Fig. 9-1 Configuration of Control Register (1/2)Note The number in parenthesis is the address used when the assembler (AS17K) is used.Colu

69µPD17062Fig. 9-1 Configuration of Control Register (2/2)89 A B C D E FSIO0CHSBSIO0MSSIO0TXBTM0CK00INTVSYNINTNCR/W R/W0IEGVSYNIEGNCBTM0ZXRSBACKSIO

7µPD170628.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ... 578.6 GENERAL-PURPOSE REGISTER POINTER (RP)...

70µPD17062Table 9-1 Peripheral Hardware Control Functions of Control Registers (1/5)Remark *: Retains the previous state.Peripheral hardwareControl

71µPD17062Table 9-1 Peripheral Hardware Control Functions of Control Registers (2/5)Remark *: Retains the previous state.Peripheral hardwareContr

72µPD17062Table 9-1 Peripheral Hardware Control Functions of Control Registers (3/5)Remark *: Retains the previous state. **: IndefinitePeriphera

73µPD17062Table 9-1 Peripheral Hardware Control Functions of Control Registers (4/5)Remark *: Retains the previous state. **: IndefinitePeriphera

74µPD17062Table 9-1 Peripheral Hardware Control Functions of Control Registers (5/5)Peripheral hardwareControl register Peripheral hardware control

75µPD17062b3b2b1b00 IDCDMAEN0000H01DMA prohibited mode (instruction cycle = 2 s)DMA mode (instruction cycle = 12 s)µµ9.1 IDCDMAEN (00H, b1)This

76µPD170629.3 CE (07H, b0)CE is a flag for reading the CE pin level.The flag indicates 1 when a high level signal is input to the CE pin, or 0 when

77µPD17062b3b2b1b0BTM0ZX BTM0CK2 BTM0CK009HBTM0CK101000001010011100101110111TIMER INT TIMER CARRY5 ms100 ms20 ms20 ms5 ms5/fTMR s5 ms6/fTMR s100 ms5 m

78µPD170629.7 INTNC (0FH, b0)The INTNC flag is used for reading the INTNC pin state.The flag indicates 1 when a high level signal is input to the IN

79µPD170629.9 PLL REFERENCE MODE SELECTION REGISTER (13H)9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H)b3b2b1b0PLLRFCK3 PLLRFCK2 PLLRFCK01

8µPD1706211.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE ... 11611.6 INTERRUPT PROCESSING ROUTINE...

80µPD170629.11 TIMER CARRY (17H)9.12 SERIAL INTERFACE WAIT CONTROL (18H)9.13 IEGNC (1FH)The IEGNC flag is used for selecting the interrupt detec

81µPD17062b3b2b1b0ADCCH2 ADCCH1 ADCCMP21HADCCH0000000110101111100110101ADC0 selectADC1 select, shared with P1C3ADC2 select, shared with P0D0ADC3 selec

82µPD170629.16 PORT1C I/O SETTING (27H)9.17 SERIAL I/O0 STATUS REGISTER (28H)b3 b2 b1 b0SIO0SF8 SIO0SF9 SBBSY28H01SBSTTBusy condition detection01S

83µPD170629.18 INTERRUPT PERMISSION FLAG (2FH)This flag is used to enable interrupt for each interrupt cause. When the flag is set to 1, interrupt

84µPD170629.20 IDCEN (31H)9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H)b3 b2 b1 b00 0 IDCEN31H010IDC operation prohibited (display off)ID

85µPD170629.22 P1BBIOn (35H)P1BBIOn specifies the PORT1B I/O. When P1BBIOn is set to 0, PORT1B becomes an input port. WhenP1BBIOn is set to 1, POR

86µPD170629.24 P0ABIOn (37H)P0ABIOn specifies the PORT0A I/O. When P0ABIOn is set to 0, PORT0A becomes an input port. WhenP0ABIOn is set to 1, POR

87µPD170629.26 SHIFT CLOCK FREQUENCY SETTING (39H)9.27 IRQNC (3FH)IRQNC is an interrupt request flag that indicates the interrupt request state.Wh

88µPD1706210. DATA BUFFER (DBF)The data buffer is used to transfer data to and from peripheral hardware and to reference tables.10.1 DATA BUFFER ST

89µPD1706210.1.2 Data Buffer StructureFig. 10-2 shows the data buffer structure.As shown in Fig. 10-2, the data buffer consists of 16 bits. Bit b0

9µPD1706217. D/A CONVERTER ... 217

90µPD1706210.2 FUNCTIONS OF DATA BUFFERThe data buffer provides the following two functions:(1) Read constant data in program memory (to reference t

91µPD1706210.3 DATA BUFFER AND TABLE REFERENCING10.3.1 Table ReferencingTables are referenced by reading the constant data from program memory int

92µPD1706210.3.2 Example Table Referencing ProgramThis section shows an example table referencing program.ExampleP0A MEM 0.70H ;P0B MEM 0.71H ;P0C M

93µPD17062This program sequentially reads the constant data stored at program memory addresses 0001H to 000CHinto the data buffer ( ) and outputs the

94µPD17062Table 10-1 Peripheral Hardware and Data Buffer FunctionsData buffer and data transferFunctionperipheral registerPeripheral hardwareName Sy

95µPD1706210.4.2 Precautions When Transferring Data With Peripheral RegistersData is transferred between the data buffer and peripheral registers in

96µPD17062Example 2. GET instructionWhen the 8-bit data of a peripheral register is read, the value of the eight high-order bits (DBF3 and DBF2)of th

97µPD1706210.5 Data Buffer and Peripheral RegistersSections 10.5.1 to 10.5.7 describe the data buffer and the peripheral registers.10.5.1 IDC Star

98µPD1706210.5.2 A/D Converter Data RegisterFig. 10-5 shows the functions of the A/D converter data register.The A/D converter data register sets th

99µPD1706210.5.3 Presettable Shift RegisterFig. 10.6 shows the functions of the presettable shift register.The presettable shift register writes the