NEC PD75P308 Manual de usuario

 NEC Corporation 1989Document No. IC-2472B(O. D. No. IC-7208C)Date Published November 1993 PPrinted in JapanDATA SHEETMOS INTEGRATED CIRCUITµPD75P30

µPD75P30810ItemµPD75P308KµPD75P308GFµPD75308GF• EPROM • PROM (one-time model) • Mask ROM• 0000H-1F7FH • 0000H-1F7FH • 0000H-1F7FH• 8064 x 8 bits • 806

µPD75P30811Pin Name FunctionVPP Applies voltage when program memory is written/verified (normally, at VDD potential)These pins input clock that update

µPD75P308123.2 PROGRAM MEMORY WRITE PROCEDUREThe program memory write procedure is as follows. High-speed program memory write is possible.(1) Groun

µPD75P308133.3 PROGRAM MEMORY READ PROCEDUREThe contents of the program memory can be read in the following procedure.(1) Ground the unused pins thr

µPD75P308143.4 ERASURE (µPD75P308K ONLY)The contents of the data programmed to the µPD75P308 can be erased by exposing the window of theprogram memor

µPD75P308154. ELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGS (Ta = 25°C)Parameter Symbol Conditions Rating UnitSupply Voltage VDD -0.3 to +7.0 VSup

µPD75P30816Ceramic*3Oscillationfrequency (fXX)*1Oscillation stabilization After VDD came to MIN.time*2of oscillation voltage rangeCrystal Oscilaltionf

µPD75P3081732 32.768 35 kHz1.0 2 s32 100 kHz515µsCrystal Oscillationfrequency (fXT)Oscillation stabilizationtime*External Clock XT1 input frequency(fX

µPD75P30818Ports 2, 3Ports 0, 1, 6, 7, RESETPorts 4, 5 Open-drainX1, X2, XT1Ports 2, 3, 4, 5Ports 0, 1, 6, 7, RESETX1, X2, XT1Ports 0, 2, 3, IOH = -1m

µPD75P30819AC CHARACTERISTICS (Ta = -10 to + 70°C, VDD = 5V ±5%)Operation Other Than Serial TransferParameter Symbol Conditions MIN. TYP. MAX. Unitw/m

µPD75P3082123456789101112131415161718192021222324S12S13S14S15S16S17S18S19S20S21S22S23S24/BP0S25/BP1S26/BP2S27/BP3S28/BP4S29/BP5S30/BP6S31/BP7COM0COM1C

µPD75P30820SERIAL TRANSFER OPERATIONTWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: internal clock output)Parameter Symbol Conditions MIN. TYP. MAX. Un

µPD75P308211600 nstKCY/2-50150 nstKCY/2 ns0 250 nstKCY nstKCY nstKCY nstKCY nsSCK Cycle TimeSCK High-, Low-LevelWidthsSB0, 1 Set-Up Time (vs. SCK )

µPD75P30822AC TIMING TEST POINT (excluding X1 and XT1 inputs)Test points0.8 VDD0.2 VDD0.8 VDD0.2 VDDCLOCK TIMINGX1 inputVDD –0.5V0.4 VtXL tXH1/fXXT1 i

µPD75P30823SERIAL TRANSFER TIMINGTHREE-LINE SERIAL I/O MODE:SCKtKL1 tKH1tKCY1Output datatSIK1 tKSI1tKSO1Input dataSISOTWO-LINE SERIAL I/O MODE:SCKtKLt

µPD75P30824SERIAL TRANSFER TIMINGBUS RELEASE SIGNAL TRANSFERRESET INPUT TIMINGINT0, 1, 2, 4KR0-7tINTLtINTHINTERRUPT INPUT TIMINGSCKtKL3,4tKCY3,4tSIK3,

µPD75P30825Released by RESETReleased by interruptLOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE(Ta = -10 to +70°C)0µs217/fX ms

µPD75P30826*1: These symbols are the corresponding µPD27C256 symbols. 2: The internal address signal is incremented by 1 at the fourth rising edge of

µPD75P30827VPPVDDVDD+1VDDMD0MD1MD2MD3VPPVDDData inputDataoutputData inputData inputtVPStVDSttDS tDHttDV tDF tDS tAHtAStOPWttM1RtPWtPCR tM1S tM1HtM3StM

µPD75P308285. PACKAGE DRAWINGSNAMFB646540KL80 PIN PLASTIC QFP (14×20)801252441GDCPdetail of lead endSQ5°±5°MIHJP80GF-80-3

µPD75P30829X80KW-80A-1ITEM MILLIMETERS INCHESNOTEEach lead centerline is located within 0.08mm (0.003 inch) of its true position (T.P.) atmaximu

µPD75P3083BLOCK DIAGRAMP00-P03P10-P13P20-P23P30-P33/MD0-MD3P40-P43P50-P53P60-P63P70-P7344444444PORT0PORT1PORT2PORT3PORT4PORT5PORT6PORT7S0-S23S24/BP0-S

µPD75P308306. RECOMMENDED SOLDERING CONDITIONSIt is recommended that µPD75P308 be soldered under the following conditions.For details on the recommen

µPD75P30831Hardare IE-75000-R*1In-circuit emulator for 75K seriesIE-75001-RIE-75000-R-EM*2Emulation board for IE-75000-R and IE-75001-REP-75308GF-R Em

µPD75P30832APPENDIX B. RELATED DOCUMENTS★

µPD75P30833GENERAL NOTES ON CMOS DEVICES1 STATIC ELECTRICITY (ALL MOS DEVICES)Exercise care so that MOS devices are not adversely influenced by static

µPD75P30834[MEMO]No part of this document may be copied or reproduced in any form or by any means without the priorwritten consent of NEC Corporation.

µPD75P3084CONTENTS1. PIN FUNCTIONS ...

µPD75P3085E-BP00 Input INT4P01 Input/Output SCKP02 Input/Output SO/SB0P03 Input/Output SI/SBIP10 INT0P11 INT1P12 INT2P13 TI0P20 PTO0P21 —P22 PCLP23 BU

µPD75P3086Timer/event counter external event pulse inputTimer/event counter outputClock outputFixed frequency output (for buzzer or for trimmingthe sy

µPD75P30871.3 PIN INPUT/OUTPUT CIRCUITSThe following shows a simplified input/output circuit diagram for each pin of the µPD75P308.TYPE A (for TYPE E

µPD75P3088P-chTYPE F–ATYPE G–CTYPE G–ATYPE G–BVDDVLC0VLC0VLC1VLC2SEGdata/Bit Port dataP-chN-chOUTN-chVLC1VLC2P-chP-chN-chOUTN-chVLC0VLC1VLC2P-chN-chSE

µPD75P3089TYPE M-CdataoutputdisableP.U.R.enableVDDP.U.R.IN/OUTP–chN-chP.U.R. : Pull–Up Resistor1.4 NOTES ON USING P00/INT4 AND RESET PINSIn addition