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NEC PD754144 manuales

Manuales del propietario y guías del usuario para Hardware NEC PD754144.
Ofrecemos 1 manuales en pdf NEC PD754144 para descargar gratis por tipos de documentos: Manual de usuario


Nec PD754144 Manual de usuario (306 paginas)


Marca: Nec | Categoria: Hardware | Tamaño: 1.81 MB |

 

Tabla de contenidos

PD754144, 754244

1

NOTES FOR CMOS DEVICES

3

Regional Information

5

INTRODUCTION

7

User’s Manual U10676EJ3V0UM

10

LIST OF FIGURES (1/3)

13

LIST OF FIGURES (2/3)

14

LIST OF FIGURES (3/3)

15

LIST OF TABLES

16

CHAPTER 1 GENERAL

17

1.1 Functional Outline

18

1.2 Ordering Information

19

1.4 Block Diagram

20

CHAPTER 1 GENERAL

21

CHAPTER 2 PIN FUNCTIONS

24

2.1 Pin Functions of

24

CHAPTER 2 PIN FUNCTIONS

26

Keep as short

29

2.3 Pin I/O Circuits

30

3.3 Memory-Mapped I/O

50

Figure 3-7

53

PD754244 I/O Map (2/8)

53

PD754244 I/O Map (3/8)

54

PD754244 I/O Map (5/8)

56

PD754244 I/O Map (6/8)

57

PD754244 I/O Map (7/8)

58

PD754244 I/O Map (8/8)

59

Figure 4-4. Data Memory Map

67

RBS (RBS = 0 to 3)

69

4.6 Accumulator

70

Remark *: Undefined

73

CHAPTER 5 EEPROM

80

5.1 EEPROM Configuration

80

5.2 EEPROM Features

80

5-1 shows its configuration

81

CHAPTER 5 EEPROM

82

6.1 Digital I/O Ports

88

Internal bus

93

0 Φ1 Φ2 Φ3

101

Selector

103

Internal bus

103

PD754144

108

• PD754244

109

PD754144

109

PD754244

109

• PD754144

109

6.4 Timer Counter

122

(a) Timer counter (channel 0)

135

(b) Timer counter (channel 1)

136

Internal clock

143

PD754244: at 4.19 MHz

155

9 ms 4.5 ms

169

REF × - AVREF ×

182

X = 4.19 MHz

182

Remark tSMP = tCY or 64/fX

194

7.4 Interrupt Sequence

197

Interrupt control instruction

202

Instruction other than

203

7.9 Application of Interrupt

204

<3> Same as <1>

208

7.10 Test Function

212

CHAPTER 8 STANDBY FUNCTION

215

CHAPTER 8 STANDBY FUNCTION

217

RESET Input Key Return Reset

221

Key return flag (KRF) 0 1

221

CHAPTER 9 RESET FUNCTION

227

CHAPTER 9 RESET FUNCTION

229

CHAPTER 10 MASK OPTIONS

233

10.1 Pin Mask Options

233

CHAPTER 11 INSTRUCTION SET

234

11.1 Unique Instructions

234

CHAPTER 11 INSTRUCTION SET

235

Note Set 0 to the B register

243

PCDE 2 3 PC11-0 ← PC11-8 + DE

245

2. Set 0 to the B register

245

MOV A, #n4

255

MOV reg1, #n4

255

MOV XA, #n8

255

MOV HL, #n8

255

MOV rp2, #n8

255

MOV A, @HL

256

MOV A, @HL+

256

MOV A, @HL–

256

MOV A, @rpa1

256

MOV XA, @HL

257

MOV @HL, A

257

MOV @HL, XA

257

MOV A, mem

257

MOV XA, mem

257

XCH A, @HL

259

XCH A, @HL+

259

XCH A, @HL–

259

XCH A, @rpa1

259

XCH XA, @HL

260

XCH A, mem

260

XCH XA, mem

260

XCH A, reg1

260

XCH XA, rp’

260

MOV XA, @PCDE

261

MOVT XA, @PCXA

263

MOVT XA, @BCDE

263

MOVT XA, @BCXA

264

ADDS A, #n4

266

ADDS XA, #n8

266

ADDS A, @HL

266

ADDS XA, rp’

266

ADDS rp’1, XA

266

ADDC A, @HL

267

ADDC XA, rp’

267

ADDC rp’1, XA

267

SUBS A, @HL

267

SUBS XA, rp’

268

SUBS rp’1, XA

268

SUBC A, @HL

268

SUBC XA, rp’

268

SUBC rp’1, XA

269

AND A, #n4

269

AND A, @HL

269

AND XA, rp’

269

AND rp’1, XA

269

OR rp’1, XA

270

XOR A, #n4

270

OR A, #n4

270

OR A, @HL

270

OR XA, rp’

270

XOR A, @HL

271

XOR XA, rp’

271

XOR rp’1, XA

271

Function: A ← A

272

BR addr1

279

BRA !addr1

279

BR !addr

279

BR $addr

279

BR $addr1

280

BRCB !caddr

280

← PC11-8 + DE

281

← D, PC3-0 ← E

281

← PC11-8 + XA

281

← X, PC3-0 ← A

281

TBR addr

282

CALLA !addr1

283

CALL !addr

283

CALLF !faddr

284

TCALL !addr

284

←rpH, (SP–2) ← rpL, SP ← SP–2

286

EI IE×××

287

DI IE×××

287

IN A, PORTn

288

OUT PORTn, A

288

GETI taddr

290

APPENDIX A DEVELOPMENT TOOLS

293

APPENDIX B ORDERING MASK ROM

297

APPENDIX C INSTRUCTION INDEX

298

APPENDIX D HARDWARE INDEX

304

APPENDIX D HARDWARE INDEX

305

APPENDIX E REVISION HISTORY

306




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